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NXP Semiconductors /LPC13xx /SYSCON /STARTERP1

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Interpret as STARTERP1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ERPIO2_8)ERPIO2_8 0 (ERPIO2_9)ERPIO2_9 0 (ERPIO2_10)ERPIO2_10 0 (ERPIO2_11)ERPIO2_11 0 (ERPIO3_0)ERPIO3_0 0 (ERPIO3_1)ERPIO3_1 0 (ERPIO3_2)ERPIO3_2 0 (ERPIO3_3)ERPIO3_3 0RESERVED

Description

Start logic signal enable register 1; top 8 interrupts

Fields

ERPIO2_8

Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, …, bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
ERPIO2_9

Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, …, bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
ERPIO2_10

Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, …, bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
ERPIO2_11

Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, …, bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled.
ERPIO3_0

Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, …, bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
ERPIO3_1

Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, …, bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
ERPIO3_2

Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, …, bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
ERPIO3_3

Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, …, bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data